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? stpc consumer-s pc compatible embeded microprocessor advanced data 1/51 29/10/99 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 1. logic diagram n powerful x86 processor n 64-bit 66mhz sdram uma controller n vga & svga crt controller n 2d graphics engine n video input port n video pipeline - up-scaler - video color space converter - chroma & colour key support n tv output - 3-line flicker filter - ccir 601/656 scan converter - ntsc / pal composite, rgb, s-video n pci master / slave controller n isa master / slave controller n integrated peripheral controller - dma controller - interrupt controller - timer / counters n optional 16-bit local bus interface n eide controller n i c interface n power management unit n 3.3v operation stpc consumer-s overview the stpc consumer-s integrates a standard 5th generation x86 core, a synchronous dram con- troller, a graphics subsystem, a video input port, video pipeline, and support logic including pci, isa, and ide controllers to provide a single con- sumer orientated pc compatible subsystem on a single device. the device is based on a tightly coupled unified memory architecture (uma), sharing the same memory array between the cpu main memory and the graphics and video frame buffers. the stpc consumer-s is packaged in a 388 plastic ball grid array (pbga). pbga388 x86 core host i/f sdram ctrl svga ge vip pci m/s lb ctr pci bus isa m/s ipc pci m/s isa bus crtc cursor monitor tv ide i/f pmu w.dog video pipeline c key k key lut local bus encoder tvo
stpc consumer-s 2/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back and write through capability. n parallel processing integral floating point unit, with automatic power down. n fully static design for dynamic clock control. n low power and system management modes. n sdram controller n 64-bit data bus. n up to 66mhz sdram clock speed. n integrated system memory, graphic frame memory and video frame memory. n supports 2mb up to 128 mb memory. n supports 8mb, 16m, and 32mb dimms. n supports buffered, non buffered, and registered dimms n 4-line write buffers for cpu to dram and pci to dram cycles. n 4-line read prefetch buffers for pci masters. n programmable latency n programmable timing for dram parameters. n supports -8, -10, -12, -13, -15 memory parts n supports 1mb up to 8mb memory hole. n 32-bit accesses not supported. n autoprecharge not supported. n power down not supported. n fpm and edo not supported. n graphics controller n 64-bit windows accelerator. n compatibility to vga & svga standards. n hardware acceleration for text, bitblts, transparent blts and fills. n up to 64 x 64 bit graphics hardware cursor. n up to 4mb long linear frame buffer. n 8-, 16-, and 24-bit pixels. n crt controller n integrated 135mhz triple ramdac allowing for 1024 x 768 x 75hz display. n 8-, 16-, 24-bit pixels. n interlaced or non-interlaced output. n video input port n accepts video inputs in ccir 601 mode. n optional 2:1 decimator n stores captured video in off setting area of the onboard frame buffer. n video pass through to the onchip pal/ntsc encoder for full screen video images. n hsync and b/t generation or lock onto external video timing source. n video pipeline n two-tap interpolative horizontal filter. n two-tap interpolative vertical filter. n color space conversion. n programmable window size. n chroma and color keying for integrated video overlay. n tv output n programmable two tap filter with gamma correction or three tap flicker filter. n progressive to interlaced scan converter. n ntsc-m, pal-m,pal-b,d,g,h,i,pal-n easy programmable video outputs. n ccir601 encoding with programmable color subcarrier frequencies. n line skip/insert capability n interlaced or non-interlaced operation mode. n 625 lines/50hz or 525 lines/60hz 8 bit multiplexed cb-y-cr digital input. n cvbs and r,g,b simultaneous analog outputs through 10-bit dacs. n cross color reduction by specific trap filtering on luma within cvbs flow. n power down mode available on each dac.
stpc consumer-s 3/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. n pci controller n fully compliant with pci 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external pal allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n pci clock is 1/3 or 1/2 host clock . n isa master/slave controller n generates the isa clock from either 14.318mhz oscillator clock or pci clock n supports programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/ o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n integrated peripheral controller n 2x8237/at compatible 7-channel dma controller. n 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n supports external rtc. n local bus interface n multiplxed with isa interface. n low latency bus n 22-bit address bus. n 16-bit data bus with word steering capability. n programmable timing (host clock granularity) n 2 programmable flash chip select. n 5 programmable i/o chip select. n supports 32-bit flash burst. n 2-level hardware key protection for flash boot block protection. n supports 2 banks of 8mb flash devices with boot block shadowed to 0x000f0000. n ide interface n supports pio and bus master ide n supports up to mode 5 timings n transfer rates to 22 mbytes/sec n supports up to 4 ide devices n concurrent channel operation (pio & dma modes) - 4 x 32-bit buffer fifo per channel n support for pio mode 3 & 4. n support for dma mode 1 & 2. n support for 11.1/16.6 mb/s, i/o channel ready pio data transfers. n supports 13.3/16.6 mb/s dma data transfers n bus master with scatter/gather capability n multi-word dma support for fast ide drives n individual drive timing for all four ide devices n supports both legacy & native ide modes n supports hard drives larger than 528mb n support for cd-rom and tape peripherals n backward compatibility with ide (ata-1). n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports smm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n supports rtc, interrupts and dmas wake-up
general description 4/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 1 general description at the heart of the stpc consumer-s is an ad- vanced 64-bit processor block, dubbed the 5st86. the 5st86 includes a 486 processor core along with a 64-bit sdram controller, advanced 64-bit accelerated graphics and video controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt control- ler, dma controller, interval timer and isa bus). the stpc consumer-s makes use of a tightly coupled unified memory architecture (uma), where the same memory array is used for cpu main memory and graphics frame-buffer. this means a reduction in total system memory for sys- tem performances that are equal to that of a com- parable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit proces- sor host interface running at the speed of the proc- essor bus rather than the traditional pci bus. the 64-bit wide memory array provides the sys- tem with 528mb/s peak bandwidth. this allows for higher resolution screens and greater color depth. the `standard' pc chipset functions (dma, inter- rupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communica- tions ports are accessed by the stpc consumer- s via internal isa bus. the pci bus is the main data communication link to the stpc consumer-s chip. the stpc con- sumer-s translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports generation of configuration cycles on the pci bus. the stpc consumer-s, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci manda- tory header registers in type 0 pci configuration space for easy porting of pci aware system bi- os. the device contains a pci arbitration function for three external pci devices. the stpc consumer-s has two functionnal blocks sharing the same balls : the isa / ipc / ide block and the local bus / ide block (see ta- ble 3). any board with the stpc consumer-s should be built using only one of these two config- urations. at reset, the configuration is done by `strap op- tions' which initialises the stpc consumer-s to the right settings. it is a set of pull-up or pull-down resistors on the memory data bus, checked on re- set, which auto-configure the stpc consumer-s. graphics functions graphics functions are controlled through the on- chip svga controller and the monitor display is produced through the 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations which include hard- ware acceleration of text, bitblts, transparent blts and fills. the results of these operations change the contents of the on-screen or off-screen frame buffer areas of dram memory. the frame buffer can occupy a space up to 4 mbytes anywhere in the physical main memory and always starts from the bottom of the main physical memory. the graphics resolution supported is a maximum of 1280x1024 in 65536 colours and 1024x768 in true color at 75hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are ex- tended by one bit to accommodate above display resolution. video functions the stpc consumer-s provides several addition- al functions to handle mpeg or similar video streams. the video input port accepts an encod- ed digital video stream in one of a number of in- dustry standard formats, decodes it, optionally decimates it, and deposits it into an off screen area of the frame buffer. an interrupt request can be generated when an entire field or frame has been captured. the video output pipeline incorpo- rates a video-scaler and color space converter function and provisions in the crt controller to display a video window. while repainting the screen the crt controller fetches both the video as well as the normal non-video frame buffer in two separate internal fifos. the video stream can be color-space converted (optionally) and smooth scaled. smooth interpolative scaling in both horizontal and vertical direction are imple- mented. color and chroma key functions are also implemented to allow mixing video stream with non-video frame buffer. the video output passes directly to the ramdac for monitor output or through another optional color space converter (rgb to 4:2:2 ycrcb) to the programmable anti-flicker filter. the flicker filter is configured as either a two line filter with gamma correction (primarily designed for dos type text) or a 3 line flicker filter (primarily designed for win- dows type displays). the fliker filter is optional and can be software disabled for use with large screen area's of video.
general description 5/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. the video output pipeline of the stpc consumer- s interfaces directly to the internal digital tv en- coder. it takes a 24 bit rgb non-interlaced pixel stream and converts to a multiplexed 4:2:2 ycrcb 8 bit output stream, the logic includes a progres- sive to interlaced scan converter and logic to in- sert appropriate ccir656 timing reference codes into the output stream. it facilitates the high quality display of vga or full screen video streams re- ceived via the video input port to standard ntsc or pal televisions. the digital pal/ntsc encoder outputs interlaced or non-interlaced video in pal-b,d,g,h,i pal-n, pal-m or ntsc-m standards and antsc- 4.43o is also possible. the four frame (for pal) or 2 frame (for ntsc) burst sequences are internally generated, subcar- rier generation being performed numerically with ckref as reference. rise and fall times of syn- chronisation tips and burst envelope are internally controlled according to the relevant itu-r and smpte recommendations. video output signals are directed to four analog output pins through internal d/a converters giving, simultaneous r,g,b and composite cvbs out- puts. ide interface an industry standard eide (ata 2) controller is built into the stpc consumer-s. the ide port is capable of supporting a total of four devices. power management the stpc consumer-s core is compliant with the advanced power management (apm) specifica- tion to provide a standard method by which the bios can control the power used by personal computers. the power management unit module (pmu) controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu pro- vides following hardware structures to assist the software in managing the power consumption by the system. - system activity detection. - three power down timers. - doze timer for detecting lack of system activity for short durations. - stand-by timer for detecting lack of system activ- ity for medium durations - suspend timer for detecting lack of system activ- ity for long durations. - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer for detecting lack of peripheral activity - susp# modulation to adjust the system perform- ance in various power down states of the system including full power on state. - power control outputs to disable power from dif- ferent planes of the board. lack of system activity for progressively longer period of times is detected by the three power down timers. these timers can generate smi in- terrupts to cpu so that the smm software can put the system in decreasing states of power con- sumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states: doze state, stand-by state and sus- pend mode. these correspond to decreasing lev- els of power savings. power down power down puts the stpc consumer-s into sus- pend mode. the processor completes execution of the current instruction, any pending decoded in- structions and associated bus cycles. during the suspend mode, internal clocks are stopped. re- moving power down, the processor resumes in- struction fetching and begins execution in the in- struction stream at the point it had stopped. be- cause of the static nature of the core, no internal data is lost.
general description 6/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 2. functionnal description. x86 core host i/f sdram i/f svga ge vip pci m/s local bus i/f pci bus isa m/s ipc 82c206 pci m/s isa bus crtc hw cursor monitor tv - pixel formating - scaler - colour space ide i/f pmu watch- video pipeline colour key chroma key lut local bus ntsc/pal encoder tvo - csc -ff - ccir ccir input
general description 7/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 3. typical application stpc consumer-s isa pci 4x 16-bit sdrams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy monitor tv video svga ccir601 ccir656 s-vhs rgb pal ntsc irq dma.req dma.ack dmux dmux mux mux rtc
general description 8/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.
update history for video controller chapter 9/51 release b 1.1 update history for video controller chapter the following changes have been made to the general description chapter on 29/10/99. section change text 1 removed athe stpc consumer-s has in addition to the 5st86 a tft output, a local bus interface, a watchdog and a jtag interface.o
pin description 10/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2 pin description 2.1 introduction the stpc consumer-s integrates most of the functionalities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devices are totally internal to the stpc consum- er-s. this offers improved performance due to the tight coupling of the processor core and these pe- ripherals. as a result many of the external pin con- nections are made directly to the on-chip peripher- al functions. figure 2.1 shows the stpc consumer-s external interfaces. it defines the main busses and their function. table 2.1 describes the physical imple- mentation listing signals type and their functionali- ty. table 2.2 provides a full pin listing and descrip- tion of pins. table 2.5 provides a full listing of pin locations of the stpc consumer-s package by physical connection. note: several interface pins are multiplexed with other functions, refer to table 2.3 and table 2.4 for further details table 2.1. signal description group name qty system clocks & resets 11 memory interface 95 pci interface 60 isa 79 89 ide 34 local bus 49 video input 11 tv output 8 vga monitor interface 8 grounds 71 v dd 29 analog specific v cc /v dd 6 total pin count 388 figure 2.1. stpc consumer-s external interfaces pci x86 sdram vga vip tv sys isa/ide/lb 95 8 11 8 60 11 89 stpc consumer-s
pin description 11/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 2.2. definition of signal pins signal name dir description qty basic clocks and resets sysrsti# i system power good input 1 sysrsto# o system reset output 1 xtali i 14.3mhz crystal input 1 xtalo i/o 14.3mhz crystal output - external oscillator input 1 hclk i/o host clock (test) 1 dev_clk o 24mhz peripheral clock (floppy drive) 1 dclk i/o 27-135mhz graphics dot clock 1 memory interface mclki i memory clock input 1 mclko o memory clock output 1 cs#[3:0] o dimm chip select 4 ma[11:0] o memory row & column address 12 md[63:0] i/o memory data 64 ras#[1:0] o row address strobe 2 cas#[1:0] o column address strobe 2 mwe# o write enable 1 dqm[7:0] o data input/output mask 8 pci interface pci_clki i 33mhz pci input clock 1 pci_clko o 33mhz pci output clock (from internal pll) 1 ad[31:0] i/o pci address / data 32 cbe#[3:0] i/o bus commands / byte enables 4 frame# i/o cycle frame 1 irdy# i/o initiator ready 1 trdy# i/o target ready 1 lock# i pci lock 1 devsel# i/o device select 1 stop# i/o stop transaction 1 par i/o parity signal transactions 1 serr# o system error 1 pcireq#[2:0] i pci request 3 pci_gnt#[2:0] o pci grant 3 pci_int[3:0] i pci interrupt request 4 vdd5 i 5v power supply for pci esd protection 4 isa control isa_clk o isa clock output - multiplexer select line for ipc 1 isa_clk2x o isa clock x2 output - multiplexer select line for ipc 1 osc14m o isa bus synchronisation clock 1 la[23:17] o unlatched address 7 sa[19:0] i/o latched address 20 sd[15:0] i/o data bus 16 ale o address latch enable 1 memr#, memw# i/o memory read and memory write 2 smemr#, smemw# o system memory read and memory write 2
pin description 12/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. ior#, iow# i/o i/o read and write 2 mcs16#, iocs16# i memory/io chip select16 2 bhe# o system bus high enable 1 zws# i zero wait state 1 ref# o refresh cycle. 1 master# i add on card owns bus 1 aen o address enable 1 iochck# i i/o channel check. 1 iochrdy i/o i/o channel ready (isa) - busy/ready (ide) 1 isaoe# o isa/ide selection 1 gpiocs# i/o general purpose chip select 1 irq_mux[3:0] i time-multiplexed interrupt request 4 dreq_mux[1:0] i time-multiplexed dma request 2 dack_enc[2:0] o encoded dma acknowledge 3 tc o isa terminal count 1 rtcas o real time clock address strobe 1 rmrtccs# i/o rom/rtc chip select 1 kbcs# i/o keyboard chip select 1 rtcrw# i/o rtc read/write 1 rtcds i/o rtc data strobe 1 local bus pa[21:0] o address bus 22 pd[15:0] i/o data bus 16 prd1#,prd0# o peripheral read control 2 pwr1#,pwr0# o peripheral write control 2 prdy# i data ready 1 fcs1#, fcs0# o flash chip select 2 iocs#[3:0] o i/o chip select 4 ide control da[2:0] o address bus 3 dd[15:0] i/o data bus 16 pcs3#,pcs1#,scs3#,scs1# o primary & secondary chip selects 4 diordy o data i/o ready 1 pirq, sirq i primary & secondary interrupt request 2 pdrq, sdrq i primary & secondary dma request 2 pdack#, sdack# o primary & secondary dma acknowledge 2 pdior#, sdior# o primary & secondary i/o channel read 2 pdiow#, sdiow# o primary & secondary i/o channel write 2 monitor interface red, green, blue o analog red, green, blue 3 vsync o vertical sync 1 hsync o horizontal sync 1 vref_dac i dac voltage reference 1 rset i resistor set 1 comp i compensation 1 table 2.2. definition of signal pins signal name dir description qty
pin description 13/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2 signal descriptions 2.2.1 basic clocks and resets sysrsti# system reset/power good. this input is low when the reset switch is depressed. other- wise, it reflects the power supply's power good signal. this input is asynchronous to all clocks, and acts as a negative active reset. the reset cir- cuit initiates a hard reset on the rising edge of this signal. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3mhz crystal input xtalo 14.3mhz crystal output. these pins are connected to the 14.318 mhz crystal to provide the reference clock for the internal frequency syn- thesizer to generate all the other clocks. a 14.318 mhz series cut crystal should be con- nected between these two pins. balance capaci- tors of 15 pf should also be added. in the event of an external quarzt oscillator providing the master clock signal to the stpc consumer-s device, the ttl signal should be provided on xtalo. hclk host clock. this clock supplies the cpu and the host related blocks. this clock can e dou- bled inside the cpu and is intended to operate in the range of 25 to 100 mhz. this clock in generat- ed internally from a pll but can be driven directly from the external system. dclk dot clock / pixel clock. this clock supplies the display controller, the video pipeline, the ram- dac, and the tv output logic. its value is depend- ent on the selected display mode. its frequency can be as high as 135 mhz. this sig- nal is either driven by the internal pll either by an external oscillator. the direction can be controlled by a strap option or an internal register bit. dev_clk 24mhz peripheral clock. this 24mhz signal is provided as a convenience for the system integration of a floppy disk driver function in an external chip. video input vclk i 27-33mhz video input port clock 1 vin i ccir 601 or 656 yuv video data input 8 vcs i/o composite synch or horizontal line sync output 1 odd_even i/o frame synchronisation 1 analog tv output red_tv, green_tv, blue_tv o analog rgb or s-vhs outputs 3 cvbs o analog video composite output 1 iref1_tv i reference current of 9bit dac for cvbs 1 vref1_tv i reference voltage of 9bit dac for cvbs 1 iref2_tv i reference current of 8bit dac for r,g,b 1 vref2_tv i reference voltage of 8bit dac for r,g,b 1 vssa_tv i analog vss for dac 1 vdda_tv i analog vdd for dac 1 miscellaneous spkrd o speaker device output 1 scl i/o i c interface - clock / can be used for vga ddc[1] signal 1 sda i/o i c interface - data / can be used for vga ddc[0] signal 1 scan_enable i reserved (test pin) 1 table 2.2. definition of signal pins signal name dir description qty
pin description 14/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2.2 memory interface mclko memory clock output. this clock is driv- ing the dimms on board and is generated from an internal pll. the default value is 66mhz. mclki memory clock input. this clock is driving the sdram controller, the graphics engine and display controller. this input should be a buffered version of the mclko signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the dimms. cs#[3:0] chip select these signals are used to disable or enable device operation by masking or enabling all sdram inputs except mclk, cke, and dqm. ma[11:0] memory address. multiplexed row and column address lines. md[63:0] memory data. this is the 64-bit memory data bus. md[40-0] are read by the device strap option registers during rising edge of sysrsti#. ras#[1:0] row address strobe. these signals enable row access and precharge. row address is latched on rising edge of mclk when ras# is low. cas#[1:0] column address strobe. these sig- nals enable column access. column address is latched on rising edge of mclk when cas# is low. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). dqm#[7:0] data mask. makes data output hi-z after the clock and masks the sdram outputs. blocks sdram data input when dqm active. 2.2.3 pci interface pci_clki 33mhz pci input clock. this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33mhz pci output clock. this is the master pci bus clock output. ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. cbe#[3:0] bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc consumer-s owns the bus and outputs when the stpc consumer-s owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc consumer-s owns the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc consumer-s initiates a bus cycle on the pci bus. it is used as an input during the pci cy- cles targeted to the stpc consumer-s to deter- mine when the current pci master is ready to complete the current transaction. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc consumer-s is the target of the current bus transaction. it is used as an input when stpc consumer-s initiates a cycle on the pci bus. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent.
pin description 15/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. devsel# i/o device select. this signal is used as an input when the stpc consumer-s initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc consumer-s is the target of the current pci transaction or when no other de- vice asserts devsel# prior to the subtractive de- code phase of the current pci transaction. stop# stop transaction. stop is used to imple- ment the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc consumer-s and is used as an output when a pci master cycle is tar- geted to the stpc consumer-s. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc consumer-s initiated pci transaction. its asser- tion by either the stpc consumer-s or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. pcireq#[2:0] pci request. this pin are the three external pci master request pins. they indi- cates to the pci arbiter that the external agents desire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it on its pcireq#. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. vdd5 5v power supply. these power pins are necessary for 5v esd protection. in case the pci bus is used in 3.3v only, these pins can be con- nected to 3.3v. 2.2.4 isa interface isa_clk, isa_clkx2 isa clock x1, x2. these pins generate the clock signal for the isa bus and a doubled clock signal. they are also used as the multiplexor control lines for the interrupt controller interrupt input lines. isa_clk is generated from either pciclk/4 or osc14m/ 2. osc14m isa bus synchronisation clock output. this is the buffered 14.318 mhz clock for the isa bus. la[23:17] unlatched address. when the isa bus is active, these pins are isa bus unlatched ad- dress for 16-bit devices. when isa bus is ac- cessed by any cycle initiated from pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are in input mode. sa[19:0] isa address bus. system address bus of isa on 8-bit slot. these pins are used as an in- put when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus. these pins are the exter- nal databus to the isa bus. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc consumer-s to indicate that la23- 17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma mas- ter or an isa master cycles by the stpc consum- er-s. ale is driven low after reset. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc con- sumer-s generates smemr# signal of the isa bus only when the address is below one megabyte or the cycle is a refresh cycle.
pin description 16/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. smemw# system memory write. the stpc con- sumer-s generates smemw# signal of the isa bus only when the address is below one mega- byte. ior# i/o read. this is the io read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the io write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. mcs16# memory chip select16. this is the de- code of la23-17 address pins of the isa address bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc consumer-s ignores this signal during io and re- fresh cycles. iocs16# io chip select16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc consumer-s does not drive iocs16# (similar to pc-at design). an isa mas- ter access to an internal register of the stpc con- sumer-s is executed as an extended 8-bit io cy- cle. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. zws# zero wait state. this signal, when assert- ed by addressed device, indicates that current cy- cle can be shortened. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc consumer-s performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a refresh cycle. the stpc consumer-s performs a pseudo hid- den refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relin- quished while the refresh cycle continues on the isa bus. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. iochrdy channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc consumer-s. the stpc consumer-s monitors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc consumer- s since the access to the system memory can be considerably delayed due uma architecture. isaoe# bidirectional oe control. this signal con- trols the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. gpiocs# i/o general purpose chip select. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the external pe- ripheral devices or any other desired function. irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they have to be encoded before connection to the stpc consumer-s using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq pin of the rtc. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc consumer-s using isaclk and isaclkx2 as the input selection strobes.
pin description 17/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc consumer-s before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.5 x-bus interface pins rtcas# real time clock address strobe. this sig- nal is asserted for any i/o write to port 70h. rmrtccs# rom/real time clock chip select. this signal is asserted if a rom access is decod- ed during a memory cycle. it should be combined with memr# or memw# signals to properly ac- cess the rom. during a io cycle, this signal is as- serted if access to the real time clock (rtc) is decoded. it should be combined with ior or iow# signals to properly access the real time clock. kbcs# keyboard chip select. this signal is as- serted if a keyboard access is decoded during a i/ o cycle. rtcrw# real time clock rw. this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcrw#. this signal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcds. this signal is asserted for any i/ o read to port 71h. note: rmrtccs#, kbcs#, rtcrw# and rtcds# signals must be ored externally with isaoe# and then connected to the external de- vice. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor as shown in figure 2.2. 2.2.6 local bus pa[21:0] address bus output. pd[15:0] data bus. this is the 16-bit data bus. d[7:0] is the lsb and pd[15:8] is the msb. pwr#[1:0] write control output. pwr0# is used to write the lsb and pwr1# to write the msb. prd#[1:0] read control output. prd0# is used to read the lsb and prd1# to read the msb. prdy# data ready input. this signal is used to create wait states on the bus. when low, it com- pletes the current cycle. fcs#[1:0] flash chip select output. these are the programmable chip select signals for up to 2 banks of flash memory. iocs#[3:0] i/o chip select output. these are the programmable chip select signals for up to 4 ex- ternal i/o devices.
pin description 18/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2.7 ide interface pcs1#, pcs3# primary chip select. these sig- nals are used as the active high primary master & slave ide chip select signals. these signals must be externally anded with the isaoe # signal be- fore driving the ide devices to guarantee it is ac- tive only when isa bus is idle. scs1#, scs3# secondary chip select. these signals are used as the active high secondary master & slave ide chip select signals. these sig- nals must be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. da[2:0] address. these signals are connected to da[2:0] of ide devices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored with isaoe# before being connected to the ide devic- es. dd[15:0] databus. when the ide bus is active, they serve as ide signals dd[11:0]. ide devices are connected to sa[19:8] directly and isa bus is connected to these pins through two ls245 trans- ceivers as described in figure 2.2. diordy busy/ready. this pin serves as ide sig- nal diordy. pirq primary interrupt request. sirq secondary interrupt request. interrupt request from ide channels. pdrq primary dma request. sdrq secondary dma request. dma request from ide channels. pdack# primary dma acknowledge. sdack# secondary dma acknowledge. dma acknoledge to ide channels. pdior#, pdiow# primary i/o read & write. sdior#, sdiow# secondary i/o read & write . primary & secondary channel read & write. 2.2.8 monitor interface red, green, blue rgb video outputs. these are the 3 analog color outputs from the ramdacs vsync vertical synchronisation pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronisation pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. an external voltage reference is connected to this pin to bias the dac. rset resistor current set. this reference cur- rent input to the ramdac is used to set the full- scale output of the ramdac. comp compensation. this is the ramdac com- pensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations.
pin description 19/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2.9 video interface vclk pixel clock input. this signal is used to syn- chronise data being transfered from an external video device to either the frame buffer, or alterna- tively out the tv output in bypass mode. this pin can be sourced from stpc if no external vclk is detected, or can be input from an external video clock source. vin[7:0] yuv video data input ccir 601 or 656. time multiplexed 4:2:2 luminance and chromi- nance data as defined in itu-r rec601-2 and rec656 (except for ttl input levels). this bus typically carries a stream of cb,y,cr,y digital vid- eo at vclk frequency, clocked on the rising edge (by default) of vclk. vcs line synchronisation output. this pin is an input in oddev+hsync or vsync + hsync or vsync slave modes and an output in all other modes (master/slave) odd_even frame synchronisation ourput. this pin supports the frame synchronisation signal. it is an input in slave modes, except when sync is extracted from ycrcbdata, and an output in mas- ter mode and when sync is extracted from ycrcb data the signal is synchronous to rising edge of dclk. the default polarity for this pin is: - odd (not-top) field : low level - even (bottom) field : high level 2.2.10 tv output red_tv / c_tv analog video outputs synchro- nized with cvbs. this output is current-driven and must be connected to analog ground over a load resistor (r load ). following the load resistor, a simple analog low pass filter is recommended. in s-vhs mode, this is the chrominance output. green_tv / y_tv analog video outputs syn- chronized with cvbs. this output is current-driv- en and must be connected to analog ground over a load resistor (r load ). following the load resis- tor, a simple analog low pass filter is recommend- ed. in s-vhs mode, this is the luminance output. blue_tv / cvbs analog video outputs synchro- nized with cvbs. this output is current-driven and must be connected to analog ground over a load resistor (r load ). following the load resistor, a simple analog low pass filter is recommended. in s-vhs mode, this is a second composite output. cvbs analog video composite output (luminance/ chrominance). cvbs is current-driven and must be connected to analog ground over a load resis- tor (r load ). following the load resistor, a simple analog low pass filter is recommended. iref1_tv ref. current for cvbs 10-bit dac. iref2_tv reference current for rgb 9-bit dac. vref1_tv ref. voltage for cvbs 10-bit dac. vref2_tv reference voltage for rgb 9-bit dac. vssa_tv analog v ss for dacs. vdda_tv analog v dd for dacs.
pin description 20/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2.11 miscellaneous spkrd speaker drive. this the output to the speaker and is and of the counter 2 output with bit 1 of port 61, and drives an external speaker driver. this output should be connected to 7407 type high voltage driver. scl, sda i c interface . these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open-collector output drivers which are internally connected to v dd through pull-up resistors. they can be used for the ddc1 (scl) and ddc0 (sda) lines of the vga interface. scan_enable reserved . the pin is reserved for test and miscellaneous functions.
pin description 21/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 2.3. isa / ide dynamic multiplexing . table 2.4. isa / local bus pin sharing . isa bus (isaoe# = 0) ide (isaoe# = 1) rmrtccs# dd[15] kbcs# dd[14] rtcrw# dd[13] rtcds dd[12] sa[19:8] dd[11:0] la[23] scs3# la[22] scs1# sa[21] pcs3# sa[20] pcs1# la[19:17] da[2:0] iochrdy diordy isa / ipc local bus sd[15:0] pd[15:0] dreq_mux[1:0] pa[21:20] smemr# pa[19] memw# pa[18] bhe# pa[17] aen pa[16] ale pa[15] memr# pa[14] ior# pa[13] iow# pa[12] ref# pa[11] iochck# pa[10] gpiocs# pa[9] zws# pa[8] sa[7:4] pa[7:4] tc, dack_enc[2:0] pa[3:0] sa[3] prdy isaoe#,sa[2:0] iocs#[3:0] dev_clk, rtcas# fcs#[1:0] iocs16#, master# prd#[1:0] smemw#, mcs16# pwr#[1:0] isaclk, isa_clk2x figure 2.2. typical isa/ide demultiplexing master# 74ls245 rmrtccs# ab dir oe isaoe# kbcs# rtcrw# rtcds sa[19:8] stpc bus / dd[15:0] la[22] la[23] la[22] la[23] scs1# scs3# pcs1# pcs3#
pin description 22/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 2.5. pinout. pin # pin name af3 sysrsti# ae4 sysrsto# a3 xtali c4 xtalo g23 hclk h24 dev_clk ad11 dclk af15 mclki ab23 mclko ae16 ma[0] ad15 ma[1] af16 ma[2] ae17 ma[3] ad16 ma[4] af17 ma[5] ae18 ma[6] ad17 ma[7] af18 ma[8] ae19 ma[9] ae20 ma[10] ac19 ma[11] af22 cs#[0] ad21 cs#[1] ae24 cs#[2] ad23 cs#[3] af23 ras#[0] ad22 ras#[1] ae21 cas#[0] ac20 cas#[1] af20 dqm#[0] ad19 dqm#[1] af21 dqm#[2] ad20 dqm#[3] ae22 dqm#[4] ae23 dqm#[5] af19 dqm#[6] ad18 dqm#[7] ac22 mwe# r1 md[0] t2 md[1] r3 md[2] t1 md[3] r4 md[4] u2 md[5] t3 md[6] u1 md[7] u4 md[8] v2 md[9] u3 md[10] v1 md[11] w2 md[12] v3 md[13] y2 md[14] w4 md[15] y1 md[16] w3 md[17] aa2 md[18] y4 md[19] aa1 md[20] y3 md[21] ab2 md[22] ab1 md[23] aa3 md[24] ab4 md[25] ac1 md[26] ab3 md[27] ad2 md[28] ac3 md[29] ad1 md[30] af2 md[31] af24 md[32] ae26 md[33] ad25 md[34] ad26 md[35] ac25 md[36] ac24 md[37] ac26 md[38] ab25 md[39] ab24 md[40] ab26 md[41] aa25 md[42] y23 md[43] aa24 md[44] aa26 md[45] y25 md[46] y26 md[47] y24 md[48] w25 md[49] v23 md[50] w26 md[51] w24 md[52] v25 md[53] v26 md[54] u25 md[55] v24 md[56] u26 md[57] u23 md[58] pin # pin name t25 md[59] u24 md[60] t26 md[61] r25 md[62] r26 md[63] f24 pci_clki d25 pci_clko b20 ad[0] c20 ad[1] b19 ad[2] a19 ad[3] c19 ad[4] b18 ad[5] a18 ad[6] b17 ad[7] c18 ad[8] a17 ad[9] d17 ad[10] b16 ad[11] c17 ad[12] b15 ad[13] a15 ad[14] c16 ad[15] b14 ad[16] d15 ad[17] a14 ad[18] b13 ad[19] d13 ad[20] a13 ad[21] c14 ad[22] b12 ad[23] c13 ad[24] a12 ad[25] c12 ad[26] a11 ad[27] d12 ad[28] b10 ad[29] c11 ad[30] a10 ad[31] d10 cbe[0] c10 cbe[1] a9 cbe[2] b8 cbe[3] a8 frame# b7 trdy# d8 irdy# a7 stop# c8 devsel# b6 par pin # pin name
pin description 23/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. d7 serr# a6 lock# d20 pci_req#[0] c21 pci_req#[1] a21 pci_req#[2] c22 pci_gnt#[0] a22 pci_gnt#[1] b21 pci_gnt#[2] a5 pci_int[0] c6 pci_int[1] b4 pci_int[2] d5 pci_int[3] a16 vdd5 b11 vdd5 b9 vdd5 d18 vdd5 f2 la[17]/da[0] g4 la[18]/da[1] f3 la[19]/da[2] f1 la[20]/pcs1# g2 la[21]/pcs3# g1 la[22]/scs1# h2 la[23]/scs3# j4 sa[0] h1 sa[1] h3 sa[2] j2 sa[3] j1 sa[4] k2 sa[5] j3 sa[6] k1 sa[7] k4 sa[8] l2 sa[9] k3 sa[10] l1 sa[11] m2 sa[12] m1 sa[13] l3 sa[14] n2 sa[15] m4 sa[16] m3 sa[17] p2 sa[18] p4 sa[19] k25 sd[0] l24 sd[1] k26 sd[2] k23 sd[3] j25 sd[4] pin # pin name k24 sd[5] j26 sd[6] h25 sd[7] h26 sd[8] j24 sd[9] g25 sd[10] h23 sd[11] d24 sd[12] c26 sd[13] a25 sd[14] b24 sd[15] ad4 isa_clk af4 isa_clk2x c9 osc14m p25 ale ae8 zws# r23 bhe# p26 memr# r24 memw# n25 smemr# n23 smemw# n26 ior# p24 iow# n24 mcs16# m26 iocs16# m25 master# l25 ref# m24 aen l26 iochck# t24 iochrdy m23 isaoe# a4 rtcas# p3 rtcds# r2 rtcrw# p1 rmrtccs# ae3 gpiocs# e23 irq_mux[0] d26 irq_mux[1] e24 irq_mux[2] c25 irq_mux[3] a24 dreq_mux[0] b23 dreq_mux[1] c23 dack_enc[0] a23 dack_enc[1] b22 dack_enc[2] d22 tc c5 spkrd n3 kbcs# pin # pin name b1 pirq c2 sirq c1 pdrq d2 sdrq d3 pdack# d1 sdack# e2 pdior# e4 pdiow# e3 sdior# e1 sdiow# af9 red ae9 green ad8 blue ac5 vsync ae5 hsync ac10 vref_dac ae10 rset ad7 comp b5 scl c7 sda ae15 vclk ad5 vin[0] af7 vin[1] af5 vin[2] ae6 vin[3] ac7 vin[4] ad6 vin[5] af6 vin[6] ae7 vin[7] ad10 red_tv af11 green_tv ae12 blue_tv ae13 vcs ac12 odd_even af14 cvbs ae11 iref1_tv af12 vref1_tv ae14 iref2_tv ac14 vref2_tv ad12 vdda_tv af8 vdd_dac1 ad9 vdd_dac2 af13 vssa_tv ac9 vss_dac1 af10 vss_dac2 pin # pin name
pin description 24/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. b3 scan_enable g24 vdd_cpuclk_pll ad13 vdd_dclk_pll f25 vdd_devclk_pll ac17 vdd_mclki_pll ac15 vdd_mclko_pll f26 vdd_hclk_pll a20 vdd c15 vdd d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd g3 vdd g26 vdd l4 vdd l23 vdd n1 vdd t4 vdd t23 vdd w1 vdd aa4 vdd aa23 vdd ac6 vdd ac2 vdd ac11 vdd ac16 vdd ac21 vdd e25 vss_dll e26 vss_dll a1:2 vss a26 vss b2 vss b25:26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss pin # pin name n4 vss n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad14 vss ad24 vss ae1:2 vss ae25 vss af1 vss af25 vss af26 vss pin # pin name
strap options 25/51 release b this is preliminary information on a new product now in developement. details are subject to change without notice 3 strap options this chapter defines the stpc consumer-s strap options and their location memory data lines note refer to designation location actual settings set to '0' set to '1' md0 1 - reserved - - - - md1 - reserved - - - - md2 - reserved - - - - md3 - reserved - - - - md4 - reserved - - - - md5 - reserved - - - - md6 - reserved - - - - md7 - reserved - - - - md8 - reserved - - - - md9 - reserved - - - - md10 - reserved - - - - md11 - reserved - - - - md12 - reserved - - - - md13 - reserved - - - - md14 - reserved - - - - md15 - reserved - - - - md16 - reserved index 4c,bit0 pull up - - md17 pci clock pci_clko divisor index 4c,bit 1 user defined hclk / 3 hclk / 2 md18 reserved index 4c,bit 2 pull up - - md19 reserved index 4c,bit 3 pull up md20 reserved index 4c, bit4 pull up - - md21 reserved index 5f, bit 0 pull up md22 reserved index 5f, bit 1 pull up md23 - reserved index 5f,bit 2 pull up - - md24 hclk hclk pll speed index 5f,bit 3 user defined 000 25 mhz md25 index 5f,bit 4 user defined 001 33 mhz md26 index 5f,bit 5 user defined 010 100 mhz 011 50 mhz 100 60 mhz 101 66 mhz 110 75 mhz 111 90 mhz md27 reserved pull down md28 reserved pull down md29 reserved pull down md30 reserved pull down md31 reserved pull down md32 reserved pull down md33 reserved pull down md34 reserved pull down md35 reserved pull down md36 reserved pull up md37 reserved pull up md38 reserved pull up
strap options 26/51 release 1.4 release b this is preliminary information on a new product now in developement. details are subject to change without notice note; 1) this strap option selects between two different functional blocks, the first is the isa and the other is the vga block. 3.1 strap register description strap option [16:0] are reserved. 3.1.1 strap register 2 index 4ch (strap2) bits 4-0 of this register reflect the status of pins md[20:16] respectively. bit 5 of this register reflect the sta- tus of pin md[23]. bit 4 is writeable, writes to other bits in this register have no effect. they are use by the chip as follows: bit 4-2; reserved bit 1; this bit reflects the value sampled on md[17] pin and controls the pci clock output as follows: 0: pci clock output = hclk / 2 1: pci clock output = hclk / 3 bit 0; reserved this register defaults to the values sampled on md[23] & md[20:16] pins after reset. 3.1.2 hclk pll strap register 0 index 5fh (hclk_strap) bits 5-0 of this register reflect the status of pins md[26:21] respectively. they are use by the chip as follows: bits 5-3 these pins reflect the value sampled on md[26:24] pins respectively and control the host clock frequency synthesizer. bit 2-0; reserved this register defaults to the values sampled on above pins after reset. md39 reserved pull up md40 cpu cpu mode user defined dx1 dx2 md41 reserved pull down md42 reserved pull down md43 reserved pull down memory data lines note refer to designation location actual settings set to '0' set to '1'
strap options 27/51 release b this is preliminary information on a new product now in developement. details are subject to change without notice 3.1.3 486 clock programming (486_clk) the bit md[40] is used to set the clock multiplication factor of the 486 core. with the md[40] pin pulled low the 486 will run in dx (x1) mode, while with the md[40] pin pulled high the 486 will run in dx2 (x2) mode. the default value of the resistor on this strap input should be a resister to gnd (dx mode). strap options [43:41] and [39:27] are reserved.
electrical specifications 28/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4 electrical specifications 4.1 introduction the electrical specifications in this chapter are val- id for the stpc consumer-s. 4.2 electrical connections 4.2.1 power/ground connections/decoupling due to the high frequency of operation of the stpc consumer-s, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc consumer-s and its output buffer cir- cuits can cause transient power surges when sev- eral output buffers switch output levels simultane- ously. these effects can be minimized by filtering the dc power leads with low-inductance decou- pling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 k w ( 10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k w ( 10%) pull-up resistor to prevent spurious operation. 4.2.3 reserved designated pins pins designated reserved should be left discon- nected. connecting a reserved pin to a pull-up re- sistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc consumer-s device. stress- es beyond those listed under table 4.1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that oper- ation under any conditions other than those spec- ified in section ooperating conditionso. exposure to conditions beyond table 4.1 may (1) reduce device reliability and (2) result in prema- ture failure even when there is no immediately ap- parent sign of failure. prolonged exposure to con- ditions at or near the absolute maximum ratings (table 4.1) may also result in reduced useful life and reliability. table 4.1. absolute maximum ratings symbol parameter value units v ddx dc supply voltage -0.3, 4.0 v v i ,v o digital input and output voltage -0.3, vdd + 0.3 v t stg storage temperature -40, +150 c t oper operating temperature 0, +70 c p tot total power dissipation 4.8 w
electrical specifications 29/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4.1 dc characteristics notes: 1. mhz ratings refer to cpu clock frequency. 2. not 100% tested. 4.1 ac characteristics table 4.4 through table 4.9 list the ac character- istics including output delays, input setup require- ments, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4.1. the rising clock edge reference level vref , and other reference levels are shown in table 4.3 below for the stpc consumer-s. input or output signals must cross these levels during testing. figure 4.1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, de- fining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. note: refer to figure 4.1. table 4.2. dc characteristics recommended operating conditions : vdd = 3.3v 0.3v, tcase = 0 to 100 c unless otherwise specified symbol parameter test conditions min typ max unit v dd operating voltage 3.0 3.3 3.6 v p dd supply power v dd = 3.3v, h clk = 66mhz 3.2 3.9 w h clk internal clock (note 1) 75 mhz v ref dac voltage reference 1.215 1.235 1.255 v v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.9 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a c in input capacitance (note 2) pf c out output capacitance (note 2) pf c clk clock capacitance (note 2) pf table 4.3. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v
electrical specifications 30/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 4.1. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd
electrical specifications 31/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 4.4. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 11 ns t2 pci_clki to frame# valid 2 11 ns t3 pci_clki to cbe#[3:0] valid 2 11 ns t4 pci_clki to par valid 2 11 ns t5 pci_clki to trdy# valid 2 11 ns t6 pci_clki to irdy# valid 2 11 ns t7 pci_clki to stop# valid 2 11 ns t8 pci_clki to devsel# valid 2 11 ns t9 pci_clki to pci_gnt# valid 2 12 ns t10 ad[31:0] bus setup to pci_clki 7 ns t11 ad[31:0] bus hold from pci_clki 0 ns t12 pci_req#[2:0] setup to pci_clki 10 ns t13 pci_req#[2:0] hold from pci_clki 0 ns t14 cbe#[3:0] setup to pci_clki 7 ns t15 cbe#[3:0] hold to pci_clki 0 ns t16 irdy# setup to pci_clki 7 ns t17 irdy# hold to pci_clki 0 ns t18 frame# setup to pci_clki 7 ns t19 frame# hold from pci_clki 0 ns table 4.5. ide bus ac timing name parameter min max unit t20 dd[15:0] setup to pior#/sior# falling 15 ns t21 dd[15:0} hold to pior#/sior# falling 12 ns table 4.6. sdram bus ac timing name parameter min max unit ns ns ns ns ns ns ns ns ns ns ns ns
electrical specifications 32/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 4.7. video input/tv output ac timing name parameter min max unit t35 video_d[7:0] setup to vclk 5 ns t36 video_d[7:0] hold from vclk 2 ns t37 vclk to vtv_bt# valid 15 ns t38 vclk to vtv_hsync valid 15 ns t39 vtv_bt# setup to vclk 10 ns t40 vtv_bt# hold from vclk 5 ns t41 vtv_hsync setup to vclk 10 ns t42 vtv_hsync hold from vclk 5 ns table 4.8. graphics adapter (vga) ac timing name parameter min max unit t43 dclk to vsync valid 45 ns t44 dclk to hsync valid 45 ns table 4.9. isa bus ac timing name parameter min max unit t45 xtalo to la[23:17] bus active 60 ns t46 xtalo to sa[19:0] bus active 60 ns t47 xtalo to bhe# valid 62 ns t48 xtalo to sd[15:0] bus active 35 ns t49 pci_clki to isaoe# valid 28 ns t50 xtalo to gpiocs# valid 60 ns t51 xtalo to ale valid 62 ns t52 xtalo to memw# valid 50 ns t53 xtalo to memr# valid 50 ns t54 xtalo to smemw# valid 50 ns t55 xtalo to smemr# valid 50 ns t56 xtalo to ior# valid 50 ns t57 xtalo to iow# valid 50 ns
mechanical data 33/51 release b 5. mechanical data 5.1 388-pin package dimension the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1. dimensions are shown in figure 5-2, table 5-1 and figure 5-3, table 5-2. figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 11 13 15 17 19 21 23 25 2468101214161820222426 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 1113151719212325 2468101214161820222426
mechanical data 34/51 release b figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c
mechanical data 35/51 release b figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g
mechanical data 36/51 release b 5.2 388-pin package thermal data 388-pin pbga package has a power dissipation capability of 4.5w which increases to 6w when used with a heatsink. structure in shown in figure 5-4. thermal dissipation options are illustrated in fig- ure 5-5 and figure 5-6. figure 5-4. 388-pin pbga structure thermal balls power & ground layers signal layers figure 5-5. thermal dissipation without heatsink ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centered on board copper thickness: -17 m m for internal layers -34 m m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the center balls
mechanical data 37/51 release b figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centered on board copper thickness: -17 m m for internal layers -34 m m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1 c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the center balls
board layout 38/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6 board layout 6.1 thermal dissipation thermal dissipation of the stpc depends mainly on supply voltage. as a result, when the system does not need to work at 3.3v, it is interresting to reduce the voltage to 3.15v for example. this may save few 100's of mw. the second area to look at is unused interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dy- namic adjustment is also a solution that can be used along with the integrated power manage- ment unit. the standard way to route thermal balls to internal ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga 388 pack- age does 90% of the thermal dissipation through the ground balls, and especially the central ther- mal balls which are directly connected to the die, the remaining 10% is dissipated through the case. adding a heat sink reduces this value to 85%. as a result, some basic rules has to be applied when routing the stpc in order to avoid thermal problems. first of all, the whole ground layer acts as a heat sink and ground balls must be directly connected to it as illustrated in figure 6-1. if one ground layer is not enough, a second ground plane may be added on solder side. figure 6-1. ground routing pad for ground ball thru hole to ground layer t o pl a y e r : s i g n a l s g r o u n dl a y e r p o w e r l a y e r b o t t o m l a y e r : s i g n a l s + l o c a l g r o u n d l a y e r ( i f n e e d e d ) note: for better visibility, ground balls are not all routed.
board layout 39/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. when considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-2. the use of a 8-mil wire results in a thermal resistance of 105 c/w assuming copper is used (418 w/ m. k). this high value is due to the thickness (34 m m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9 c/w. this can be easily im- proved using four 10 mil wires to connect to the four vias around the ground pad link as in figure 6-3. this gives a total of 49 vias and a global re- sistance for the 36 thermal balls of 0.6 c/w. the use of a ground plane like in figure 6-4 is even better. to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad), this gives a di- ameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no lo- cal boar d distortion is tolerated. the thickness of the copper on pcb layers is typ- ically 34 m m for external layers and 17 m m for inter- nal layers. that means thermal dissipation is not good and temperature of the board is concentrat- ed around the devices and falls quickly with in- creased distance. when it is possible to place a metal layer inside the pcb, this improves dramatically the heat spreading and hence thermal dissipation of the board. figure 6-2. recommended 1-wire ground pad layout figure 6-3. recommended 4-wire ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 10 mil) via (diameter = 24 mil) 34.5 mil 1 mil = 0.0254 mm 4 via pads for each ground ball
board layout 40/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. the pbga package dissipates also through pe- ripheral ground balls. when a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipa- tion through the peripheral ground balls. the more via pads are connected to each ground ball, the more heat is dissipated . the only limita- tion is the risk of lossing routing channels. figure 6-5 shows a routing with a good trade off between thermal dissipation and number of rout- ing channels. figure 6-4. optimum layout for central ground ball via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil figure 6-5. global ground layout for good thermal dissipation ground pad via to ground layer
board layout 41/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. a local ground plane on opposite side of the board as shown in figure 6-6 improves thermal dissipa- tion. it is used to connect decoupling capacitances but can also be used for connection to a heat sink or to the system's metal box for better dissipation. this possibility of using the whole system's box for thermal dissipation is very usefull in case of high temperature inside the system and low tempera- ture outside. in that case, both sides of the pbga should be thermally connected to the metal chas- sis in order to propagate the heat flow through the metal. figure 6-7 illustrates such implementation. figure 6-6. bottom side layout and decoupling ground plane for thermal dissipation via to ground layer figure 6-7. use of metal plate for thermal dissipation metal planes thermal conductor board die
board layout 42/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.2 high speed signals some interfaces of the stpc run at high speed and have to be carefully routed or even shielded. here is the list of these interfaces, in decreasing speed order: 1) memory interface. 2) graphics and video interfaces 3) pci bus 4) 14mhz oscillator stage all the clocks haves to be routed first and shielded for speeds of 27mhz or more. the high speed sig- nals follow the same contrainsts, like the memory control signals and the pci control signals. the next interfaces to be routed are memory, vid- eo/graphics, and pci. all the analog noise sensitive signals have to be routed in a separate area and hence can be rout- ed indepedently. figure 6-8. shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines
board layout 43/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3 memory interface 6.3.1 introduction in order to achieve sdram memory interfaces which work at clock frequencies of 66mhz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. the guidelines described below are related to sdram components on dimm modules. for ap- plications where the memories are directly sol- dered to the motherboard, the pcb should be laid out such that the trace lengths fit within the con- straints shown here. the traces could be slightly longer since the extra routing on the dimm pcb is no longer present but it is then up to the user to verify the timings. 6.3.2 sdram clocking scheme the sdram clocking scheme deserves a special mention here. basically the memory clock is gen- erated on-chip through a pll and goes directly to the mclko output pin of the stpc. the nominal frequency is 66mhz. because of the high load presented to the mclk on the board by the dimms it is recommeded to rebuffer the mclko signal on the board and balance the skew to the clock ports of the different dimms and the mclki input pin of stpc. figure 6-9. clock scheme dimm1 mclki mclko dimm2 pll register pll ma[] + control md[]
board layout 44/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.3 board layout issues the physical layout of the motherboard pcb as- sumed in this presentation is as shown in figure 6-10. because all the memory interface signal balls are located in the same region of the stpc device it is possible to orientate the device to re- duce the trace lengths. the worst case routing length to the dimm1 is estimated to be 100mm. solid power and ground planes are a must in order to provide good return paths for the signals and to reduce emi and noise. also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change layers. if possible the traces should be routed adjacent to the same power or ground plane for the length of the trace. for the sdram interface the most critical signal is the clock. any skew between the clocks at the sdram components and the memory controller will impact the timing budget. in order to get well matched clocks at all the components it is recom- mended that all the dimm clock pins, stpc mem- ory clock input (mclki) and any other component using the memory clock are individually driven from a low skew clock driver with matched routing lengths. this is shown in figure 6-11. the maximum skew between pins for this part is 250ps. the important factors for the clock buffer are a consistent drive strength and low skew be- tween the outputs. the delay through the buffer is not important so it does not have to be a zero de- lay pll type buffer. the trace lengths from the clock driver to the dimm ckn pins should be matched exactly. since the propagation speed can vary be- tween pcb layers the clocks should be routed in a consistent way. the routing to the stpc memory input should be longer by 75mm to compensate for the extra clock routing on the dimm. also a 20pf capacitor should be placed as near as pos- sible to the clock input of the stpc to compensate for the dimm's higher clock load. the impedance of the trace used for the clock routing should be matched to the dimm clock trace impedance (60- 75w ). to minimise crosstalk the clocks should be routed with spacing to adjacent tracks of at least twice the clock trace width. for designs which use sdrams directly mounted on the moth- erboard pcb all the clock trace lengths should be matched exactly. the dimm sockets should be populated starting with the furthest dimm from the stpc device first (dimm1). there are 2 types of dimm devices; sin- gle row and dual row. the dual row devices re- quire 2 chip select signals to select between the two rows. a stpc device with 4 chip select control lines could control either 4 single row dimms or 2 dual row dimms. figure 6-10. dimm placement dimm4 dimm3 dimm2 dimm1 stpc 35mm 35mm 15mm 10mm 116mm sdram i/f
board layout 45/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. when using dimm modules, schematics have to be done carefully in order to avoid data busses completely crossed on the board. this has to be checked at the library level. in order to achive lay- out shown in figure 6-12, schematics have to im- plement the crossing described on figure 6-13. the dqm signals must be exchanged using the same order. figure 6-11. clock routing mclko dimm ckn input stpc mclki dimm ckn input dimm ckn input low skew clock driver: l l+75mm* 20pf * no additionnal 75mm when sdram directly soldered on board figure 6-12. optimum data bus layout for dimm figure 6-13. schematics for optimum data bus layout for dimm dimm stpc sdram i/f d[15:00] d[31:16] d[47:32] d[63:48] md[31:00] md[63:32] md[15:00],dqm[1:0] md[31:16],dqm[3:2] md[47:32],dqm[5:4] md[63:48],dqm[7:6] d[15:00],dqm[1:0] d[31:16],dqm[3:2] d[47:32],dqm[5:4] d[63:48],dqm[7:6] dimm stpc
board layout 46/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.4 address & control signals this group encompasses the memory address ma[12:0], bank address ba[0,1], ras, cas and write enable we signals. the load of the dimm module on these signals is the most important oneand depends upon the type of sdram com- ponents used (x4, x8 or x16) and whether the dimm module is single or dual row. the capacitive loading of the sdram inputs alone for an x8 sin- gle row dimm will be about 30-40pf. an equiva- lent circuit for the timing simulation is shown in figure 6-14 most of the delays are due to the pcb traces and loading rather than the pad itself. 6.3.5 chip select signals (cs#[3:0]) there are 4 chip select pins per dimm. chip se- lects 0 and 2 are always used to select the first row of sdrams and chip selects 1 and 3 select the second row on dual bank sdrams. the chip select outputs only have to drive one dimm each 6.3.6 data write (md[63:0]) the load on the data signals is much lower than the address/control signals for an unbuffered dimm. for a registered dimm the data signals are the only memory pins of the dimm which are not registered. for the design to get maximum benefit from using registered dimms the timings should be compared to the timings for registered dimms for the other pins.. figure 6-14. address/control equivalent circuit dimm4 dimm3 dimm2 dimm1 rterm 100mm (0.7ns) 10mm z pcb figure 6-15. cs# equivalent circuit 130mm (0.9ns) dimm cs[0] cs[2] figure 6-16. data write equivalent circuit dimm4 dimm3 dimm2 dimm1 125mm (0.9ns) 10mm
board layout 47/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.7 data read (md[63:0]) the data read simulation circuit is shown below.. 6.3.8 data mask (dqm[7:0]) the data mask load is quite similar to that of the data signals. 6.3.9 summary for unbuffered dimms the address/control signals will be the most critical for timing unless the mem- ory controller can be designed to set up these sig- nals one cycle in advance. the simulations show that for these signals the best way to drive them is to use a parallel termination. for applications where speed is not so critical series termination can be used as this will save power. using a low impedance such as 50w for these critical traces is recommended as it both reduces the delay and the overshoot. the other memory interface signals will typically be not as critical as the address/control signals for unbuffered dimms. when using registered dimms the other signals will probably be just as critical as the address/control signals so to gain maximum benefit from using registered dimms the timings should also be considered in that situation. using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control signals they could use the de- fault value. using a lower impedance implies us- ing wider traces which may have an impact on the routing of the board. figure 6-17. data read equivalent circuit 125mm (0.9ns) dimm2 dimm3 dimm4 10mm 10w sdram dq dimm1
ordering data 48/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 7 ordering data 7.1 ordering codes st pc c03 66 bt c 3 stmicroelectronics prefix product family pc: pc compatible product id c03: consumer-s core speed 66: 66mhz 75: 75mhz package bt: 388 overmoulded bga temperature range c: commercial case temperature (tcase) = 0 c to +100 c i: industrial case temperature (tcase) = -40 c to +100 c operating voltage 3 : 3.3v 0.3v
ordering data 49/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 7.2 available part numbers part number core frequency ( mhz ) cpu mode (dx/dx2) tcase range ( c) operating voltage (v) stpcc0366btc3 66 dx 0 cto+100 3.3v 0.3v stpcc0375btc3 75 dx stpcc0390btc3 90 dx stpcc0310btc3 100 dx stpcc0366btc3 66 dx -40 c to +100
ordering data 50/51 release b this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. ? 1999 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 51 release b

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